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[ARM-PowerPC-ColdFire-MIPS] embedded_risc

Description: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Platform: | Size: 128000 | Author: 箫勇天 | Hits:

[VHDL-FPGA-Verilog] CPUverilog

Description: pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.
Platform: | Size: 24576 | Author: 詹伟业 | Hits:

[Other Embeded program] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 38912 | Author: wl | Hits:

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

[Other Embeded program] pcit32_verilog_lattice

Description: 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
Platform: | Size: 430080 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] parity2258

Description: 奇偶校验码的VERILOG源码，为MODELSIM下的一个工程。有测试文件。-parity VERILOG source code for MODELSIM of a project. A test document.
Platform: | Size: 25600 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] VERcf_fft_1024_8

Description: 1024点８位FFT的Verilog语言实现-1024-point FFT eight Verilog language
Platform: | Size: 11264 | Author: 郭子荣 | Hits:

[VHDL-FPGA-Verilog] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 15360 | Author: 姚卫忠 | Hits:

[VHDL-FPGA-Verilog] yimazhenque

Description: 47译码器器的verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Platform: | Size: 21504 | Author: 刘东辉 | Hits:

[VHDL-FPGA-Verilog] lpm_mul

Description: ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Platform: | Size: 27648 | Author: 刘东辉 | Hits:

[Software Engineering] risc8

Description: 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
Platform: | Size: 82944 | Author: snake | Hits:

[VHDL-FPGA-Verilog] Viterbi_v

Description: Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
Platform: | Size: 11264 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] cache

Description: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Platform: | Size: 4096 | Author: MingCheng | Hits:

[SCM] verilog_cpu

Description: 一个小单片机的verilog源代码, 包含说明文档-a small SCM verilog source code contains documentation
Platform: | Size: 16384 | Author: Charles Wen | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] video_in

Description: 一个视频信号输入的verilog源代码，里面含有相关的使用文档。-A video signal input of the Verilog source code, which contains documents related to the use.
Platform: | Size: 339968 | Author: ln | Hits:

[ARM-PowerPC-ColdFire-MIPS] verilog

Description: LEON（sparc）微处理器的源代码，有志于微处理器开发的多交流-LEON (sparc) the source code of the microprocessor, the microprocessor is interested in the development of multi-exchange
Platform: | Size: 212992 | Author: caianning | Hits:

[VHDL-FPGA-Verilog] S6_VGA_change

Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Platform: | Size: 2572288 | Author: 李晨 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:
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